NVIDIA Interview Report
- -1of 1 vote
Answers1) Design a synchronous circuit which follows this pattern:
- AJ February 22, 2008
1000
1100
1110
1111
0111
0011
0001
0000
1000
Is it possible to design this circuit if there is no reset. If yes then how?
2) Design a circuit which generates the following pattern:
1000
0100
0010
0001
0010
0100
1000
3) In the above mentioned question how many FF's are least required? Justify your answer!
4)Generate the above mentioned pattern by using only combinational logic and D FF.| Report Duplicate | Flag | PURGE
NVIDIA Software Engineer / Developer Computer Architecture & Low Level - 0of 0 votes
AnswersLet suppose there is a FIFO. Data is written into the FIFO at the speed of 4 ns. A maximum
- AJ July 22, 2008
of 80 words /100 cycle are expected. The read port reads the data at the speed of 5ns. It
can read 80 words/ 80 cycles. What should be the depth of the FIFO so that we dont lose any
data. Hint: Consider the previous cycle as well| Report Duplicate | Flag | PURGE
NVIDIA Software Engineer / Developer Computer Architecture & Low Level